An essential task for a designer of Large Scale Integrated (LSI) circuits is to maximize the density of useful gates. Since an I/O circuit constitutes a significant portion of the available area on an integrated circuit chip, optimizing I/O design is an important step in achieving a higher gate density or a smaller die size.
An I/O circuit normally consists of a combination of several subcomponents including an output control drive circuit (for output), a receiver circuit (for input) and a electrostatic discharge protection (ESD) circuit. While most I/O circuits are similar in principle, the number and size of gates used can be significantly different depending on the required drive strength. The area that an I/O circuit occupies on the chip surface of the die thus differs significantly.
When choosing a die size, a designer may come across three situations. In the first situation, the function of the chip is complicated while the number of I/O pins is small. The die thus must be large enough to accommodate all the gates while the I/O is not a factor. Optimizing core area gate density is vital in minimizing die size in this situation. Another situation is when the function on the chip is relatively simple, but a large number of I/O pins are required. The die size may thus be limited by the placement of I/O cells and bonding pads. The "bonding pad rule" requires that the bonding pad spacing be larger than a certain minimum dimension. While the bonding pads are placed along the edge of the die, a large number of pads may require a large die perimeter, and thus a large die. The third situation is that the number of gates and the number of pins are comparably demanding on the die size. In the last two situations optimizing I/O design is vitally important.
One prior art technique for I/O design is the "reserve cell" technique. The designer sets aside a predetermined outer ring area of the die for I/O use. The ring area is divided into numerous slots that are equal in width. A slot is further divided into fine grids. Each I/O cell constitutes one or more I/O slots.
FIG. 1a shows a rim portion of a semiconductor integrated circuit die using prior art "reserve cell" technique. In the center of the die is the core area 4. Along the edge is the I/O ring which consists of I/O slots 2 and an area for bonding pads 3. The I/O slots are equal in width. At the lower left corner of each slot 2 is the origin mark 9, which by custom in the industry is seen to be a customized "F" on integrated circuit schematic diagrams. For each slot a bonding pad is placed directly below the origin mark. During the initial stage of circuit design, the engineer would estimate the number and size of circuit devices required for a particular I/O circuit based on the drive strength. He/she then estimates the required area for that particular circuit. Since all slots are of equal height, the engineer can then calculate the width of the cell. Knowing the width of each slot and the required width of the cell, the engineer can then determine the number of slots that are needed for that cell. When the I/O circuit is so small that the cell width required is less than the width of a slot, then a single slot is used as a "cell" for that circuit. On the other hand, when the width of a circuit is more than one slot, however, multiple slots must be combined to form a cell for that circuit. Each cell must constitute an integer number of slots. In other words, the smallest cell area unit is a slot.
FIG. 1b shows the same section of the die when the slots are combined to form cells 25. The first two cells are made of two slots each while the third cell constitutes three slots. There are two major drawbacks in this technique. The first is that much space in the I/O cell is wasted. For example, if a particular I/O circuit needs the space in the chip equal to one and a half slots, two slots will be assigned for that cell because the smallest integer number of slots that can accommodate the circuit is two. In the worst scenario, therefore, an area slightly less than a whole slot is wasted in each cell. The second drawback is bonding pad waste. As stated above, each slot has one bonding pad associated with it. For the first cell in FIG. 1b, two pads, 100 and 101, are set aside for the cell. Since each I/O cell normally requires one bonding pad, however, only bonding pad 100 is used while 101 is unused and, therefore, wasted.
The wasted I/O cell problem can be partially solved by the "integrated function" technique. When this technique is used no specific I/O area is set aside. The designer integrates the I/O circuits into the functional circuits so that "corners" left by one circuit are used by another. Because of the fully custom nature, this technique allows the designer to achieve very high gate densities. A drawback of this technique is that it is labor intensive and is not suitable for situations where a short turn-around time is essential.
When the density is controlled by the placement of bonding pads, and optimizing pad usage is necessary, the technique disclosed in U.S. Pat. No. 4,947,233, can be employed. Using this technique, one I/O cell can contain two sets of I/O circuits, and is connected to two bonding pads. While this technique aims at solving the problem of bonding pad over-crowdedness, to some extent it also helps to improve the gate density in the I/O area. When an engineer or designer has an option to fit either one or two I/O circuits into one cell, it is more likely to fill up the available area. In cases where the drive strength requirement is low, however, two circuits may occupy only a portion of the cell, leaving a large portion unused.
A solution proposed in U.S. Pat. Nos. 5,045,913 and 4,988,636, is the "ring integration" approach. Instead of designing I/O circuits individually, as is done traditionally, this method teaches designing like components of several circuits together. The designer or engineer will break several I/O circuits into components and then sort like components into groups. When like components are stacked next to each other, a mutual N-guard ring or P-guard ring can be used to replace the discrete N-guard wells or P-guard wells. For example, when several N channel driving devices are designed separately, each one needs a separate N guard well. By placing several N channel driving devices closely together in a row, one N guard ring can be shared by all the devices. Since this method arranges similar devices into banks, it is most suitably used with gate array technology. For non-gate array chips, however, since a fully custom design may require certain irregularities, this technique can not be used effectively.
An improvement over the original "reserved cell" technology is the "reduced cell" technology, where the height of a cell is reduced to about 55% of the regular "reserve cell". In reducing the height, the internal core area is increased directly proportional to the reduction done to the height of the I/O's. A draw back of this technique is that when the height of the I/O cell is reduced, the reduced real state of the I/O area may be too small to accommodate all the implementations a designer would like to have.
It is, therefore, the intent of the present invention to optimize I/O cell design without additional labor. With the technique as presented herein, no bonding pad is assigned unless necessary and an I/O cell is just large enough for the particular implementation. This invention presents such a technique.